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document no. doc-15014-3 www.psemi.com page 1 of 13 ?2010-2013 peregrine semiconductor corp. all rights reserved. peregrine?s PE33241 is a high-performance integer-n pll capable of frequency synthesis up to 5 ghz. the device is designed for superior phase noise performance with a direct or serial programming option. the PE33241 features a selectable prescaler modulus of 5/6 or 10/11, counters and a phase comparator as shown in figure 1 . counter values are programmable through either a serial interface or directly hard-wired. the PE33241 is available in a 48-lead 7x7 mm qfn and is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering excellent rf performance. preliminary specification ultracmos ? integer-n pll frequency synthesizer for low phase noise applications product description PE33241 features ?? frequency range ?? 5 ghz in 10/11 prescaler modulus ?? 4 ghz in 5/6 prescaler modulus ?? phase noise floor figure of merit: -230 dbc/hz ?? selectable prescaler modulus of 5/6 or 10/11 ?? low power: 80 ma at 2.8v ?? serial or direct mode access ?? internal phase detector ?? packaged in a 48-lead 7x7 mm qfn figure 1. functional diagram applications ?? industrial applications ?? military applications ?? point-to-point radios ?? cellular base stations ?? catv equipment reference divider phase detector prescaler 5/6 ? or 10/11 loop ? filter vco rf out f in f ref main ? counter control logic serial control f c f p direct control PE33241
preliminary specification PE33241 page 2 of 13 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. doc-15014-3 ultracmos ? rfic solutions table 1. pin descriptions figure 2. pin configurations (top view) figure 3. package type 48-lead 7x7 mm qfn pin no. pin name interface mode type description 1 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 2 r4 direct input r counter bit 4 3 r5 direct input r counter bit 5 4 a3 direct input a counter bit 3 5 n/c both note 3 no connect 6 gnd both ground 7 m3 direct input m counter bit 3 8 m2 direct input m counter bit 2 9 m1 direct input m counter bit 1 10 m0 direct input m counter bit 0 11 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 12 gnd both ground 13 m8 direct input m counter bit 8 14 m7 direct input m counter bit 7 15 sclk serial input serial clock input. sdata is clocked serially into the 20-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e _wr ?high?) on the rising edge of sclk m6 direct input m counter bit 6 16 sdata serial input binary serial dat a input. input data entered msb first m5 direct input m counter bit 5 s_wr serial input serial load enable input. while s_wr is ?low?, sdata can be serially clocked. primary register data is transferred to the secondar y register on s_wr or hop_wr rising edge m4 direct input m counter bit 4 17
preliminary specification PE33241 page 3 of 13 document no. doc-15014-3 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. table 1. pin descriptions (continued) pin no. pin name interface mode type description 18 gnd both ground 19 direct direct input select ?high? enables di rect mode. select ?low? enables serial mode 20 a0 direct input a counter bit 0 e_wr serial input enhancement register write enable. while e_ wr is ?high?, sdata can be serially clocked into the enhancement register on the rising edge of sclk a1 direct input a counter bit 1 22 a2 direct input a counter bit 2 23 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 24 n/c both note 3 no connect 25 pre_en direct input prescaler enable, active ?low?. when ?high?, f in bypasses the prescaler 26 pre_5/6_sel direct input 5/6 modulus select, ac tive ?high.? when ?low,? 10/11 modulus selected 27 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 28 f ? in both input prescaler complementary input. a 22 pf by pass capacitor should be placed as close as possible to this pin and be connected in series with a 50 resistor to ground 29 f in both input prescaler input from the vco, 5 ghz max frequency. a 22 pf coupling capacitor should be placed as close as possible to this pin and be connected in shunt to a 50 ? resistor to ground 30 gnd both ground 31 dout serial output data out. the msel signal and the raw prescaler output are available on dout through enhancement register programming 32 cext both output logical ?nand? of pd_ d and pd_ u terminated through an on chip, 2 k ? series resistor. connecting cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld 33 ld both output lock detect and open drain logical inversion of cext. when the loop is in lock, ld is high impedance, otherwise ld is a logic low (?0?) 34 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 35 pd_ d ? both output pd_ d is pulse down when f p leads f c 36 pd_ u ? both output pd_ u is pulse down when f c leads f p 37 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 38 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 39 f r both input reference frequency input 40 v dd both note 1 power supply input. input may range from 2.65 to 2.95v. bypassing recommended 41 enh serial input enhancement mode. when asserted low (?0?), enhancement register bits are functional 42 gnd both ground 43 n/c both note 3 no connect 44 r0 direct input r counter bit 0 45 r1 direct input r counter bit 1 46 r2 direct input r counter bit 2 47 r3 direct input r counter bit 3 48 gnd both ground 21 notes: 1. v dd pins 1, 11, 23, 27, 34, 37, 38 and 40 are connected by diodes and must be supplied with the same positive voltage level 2. all digital input pins have 70 k ? pull-down resistors to ground 3. no connect pins can be left open or floating
preliminary specification PE33241 page 4 of 13 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. doc-15014-3 ultracmos ? rfic solutions table 2. absolute maximum ratings note 1: periodically sampled, not 100% tested. tested per mil-std-883, m3015 c2 table 4. esd ratings electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. table 3. operating ratings table 5. dc characteristics: v dd = 2.65 to 2.95v, -40c < t a < 85c, unless otherwise specified symbol parameter/condition min max unit v dd supply voltage -0.3 3.3 v v i voltage on any input -0.3 v dd + 0.3 v i i dc into any input -10 +10 ma i o dc into any output -10 +10 ma t stg storage temperature range -65 150 c symbol parameter/condition level unit v esd esd voltage (human body model) 1 1000 v symbol parameter/condition min max unit v dd supply voltage 2.65 2.95 v t a operating ambient temperature range -40 85 ? c symbol parameter condition min typ max unit i dd operational supply current pre_5/6_sel = ?low? prescaler disabled 40 ma prescaler enabled 80 ma digital inputs: all except f r , f in , f ? in v ih high level input voltage 0.7 x v dd v v il low level input voltage 0.3 x v dd v i ih high level input current v ih = v dd = 2.95v 70 a i il low level input current v il = 0, v dd = 2.95v -1 a reference divider input: f r i ihr high level input current v ih = v dd = 2.95v 100 a i ilr low level input current v il = 0, v dd = 2.95v -100 a counter and phase detector outputs: pd_ d , pd_ u v old output voltage low i out = 6 ma 0.4 v v ohd output voltage high i out = -3 ma v dd - 0.4 v lock detect outputs: cext, ld v olc output voltage low, cext i out = 100 a 0.4 v v ohc output voltage high, cext i out = -100 a v dd - 0.4 v v olld output voltage low, ld i out = 1 ma 0.4 v fc = 50 mhz, fin = 500 mhz fc = 50 mhz, fin = 3 ghz moisture sensitivity level the moisture sensitivity level rating for the PE33241 in the 48-lead 7x7 mm qfn package is msl3.
preliminary specification PE33241 page 5 of 13 document no. doc-15014-3 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. table 6. ac characteristics: v dd = 2.65 to 2.95v, -40c < t a < 85c, unless otherwise specified symbol parameter condition min typical max unit control interface and latches (see figures 4, 5, 6 ) f clk serial data clock frequency 1 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t dsu sdata set-up time after sclk rising edge, d[7:0] set-up time to m1_wr, m2_wr, a_wr, e_wr rising edge 10 ns t dhld sdata hold time after sclk rising edge, d[7:0] hold time to m1_wr, m2_wr, a_wr, e_wr rising edge 10 ns t pw s_wr, m1_wr, m2_wr, a_wr, e_wr pulse width 30 ns t cwr sclk rising edge to s_wr rising edge. s_wr, m1_wr, m2_wr, a_wr falling edge to hop_wr rising edge 30 ns t ce sclk falling edge to e_wr transition 30 ns t wrc s_wr falling edge to sclk rising edge. hop_wr falling edge to s_wr, m1_wr, m2_wr, a_wr rising edge 30 ns t ec e_wr transition to sclk rising edge 30 ns t mdo msel data out delay after f in rising edge c l = 12 pf 8 ns main divider 10/11 (including prescaler) 4 p fin input level range external ac coupling 800 mhz freq < 1200 mhz 1200 mhz freq 5 ghz 0 -3 5 5 5 dbm dbm main divider 5/6 (including prescaler) 4 p fin input level range external ac coupling 800 mhz freq < 1200 mhz 1200 mhz freq 4 ghz 0 -3 5 5 5 dbm dbm main divider (prescaler bypassed) 4 f in operating frequency 2 50 800 mhz p fin input level range external ac coupling -5 5 5 dbm reference divider f r operating frequency 3 100 mhz p fr reference input power 2 single-ended input -5 6 7 dbm phase detector f c comparison frequency 3 100 mhz
preliminary specification PE33241 page 6 of 13 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. doc-15014-3 ultracmos ? rfic solutions table 6. ac characteristics: v dd = 2.65 to 2.95v, -40c < t a < 85c, unless otherwise specified (continued) symbol parameter condition min typical max unit ssb phase noise 5/6 prescaler (f in = 3 ghz, f c = 50 mhz, lbw = 500 khz) ? n ? phase noise 100 hz offset -95 dbc/hz ? n ? phase noise 1 khz offset -102 dbc/hz ? n ? phase noise 10 khz offset -112 dbc/hz ? n ? phase noise 100 khz offset -116 dbc/hz ssb phase noise 10/11 prescaler (f in = 3 ghz, f c = 50 mhz, lbw = 500 khz) ? n ? phase noise 100 hz offset -92 dbc/hz ? n ? phase noise 1 khz offset -99 dbc/hz ? n ? phase noise 10 khz offset -109 dbc/hz ? n ? phase noise 100 khz offset -114 dbc/hz phase noise figure of merit (fom) fom flicker flicker figure of merit 5/6 prescaler -263 dbc/hz 10/11 prescaler -260 dbc/hz fom floor floor figure of merit 5/6 prescaler -230 dbc/hz 10/11 prescaler -228 dbc/hz fom flicker pn flicker = fom flicker + 20log (f vco ) - 10log (f offset ) dbc/hz fom floor pn floor = fom floor + 10log (f pfd ) + 20log (f vco /f pfd ) dbc/hz fom total dbc/hz pn total = 10log (10 [pn flicker /10] + 10 [pn floor /10]) notes: 1. fclk is verified during the functional pattern te st. serial programming sections of the functional pattern are cloc ked at 10 mhz to verify fclk specification 2. cmos logic levels can be used to drive the reference input. if the v dd of the cmos driver matches the v dd of the pll ic, then the reference input can be dc coupled. otherwise, the reference input should be ac coupled. fo r sine-wave inputs, the minimum amplitude needs to be 0.5 vpp. the maximum level should be limited to prevent esd diodes at the pin input from turning on. diodes will turn on at one forward-bias diode drop above v dd or below gnd. the dc voltage at the reference input is v dd /2 3. parameter is guaranteed through characterization only and is not tested 4. parameters below are not tested for die sales. thes e parameters are verified during the element evaluation 5. 0 dbm minimum is recommended for improved pha se noise performance when sine-wave is applied 6. +2 dbm or higher is recommended for improved phase noise performance
preliminary specification PE33241 page 7 of 13 document no. doc-15014-3 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. functional description the PE33241 consists of a prescaler, counters, a phase detector, and control logic. the dual modulus prescaler divides the vco frequency by either 5/6 or 10/11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 21-bit register. an additional counter (?a?) is used in the modulus select logic. the phase-frequency detector generates up and down frequency control signals. the control logic includes a selectable chip interface. data can be written via serial bus or hardwired directly to the pins. there are also various operational and test modes and a lock detect output. figure 4. functional block diagram prescaler 5/6 or 10/11 main counter m(8:0) a(3:0) r(5:0) 20 20 r counter phase detector 6 6 13 pd_u pd_d msel prescaler enable select sdata s_wr sclk secondary 20-bit latch primary 21-bit latch input buffer pre_5/6_sel pre_en cext input buffer ld f p f c fr direct v dd gnd enh register 8-bit 8 e_wr sdata sclk enh dout f c f p msel 8 direct mode serial mode f in f in
preliminary specification PE33241 page 8 of 13 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. doc-15014-3 ultracmos ? rfic solutions main counter chain normal operating mode the main counter chain divides the rf input frequency, f in , by an integer derived from the user- defined values in the ?m? and ?a? counters. it is composed of the 5/6 or 10/11 selectable modulus prescaler, modulus select logic, and 9-bit m counter. the prescaler can be set to either 5/6 or 10/11 based on the pre_5/6_sel pin. setting pre_en ?low? enables the 5/6 or 10/11 prescaler. setting pre_en ?high? allows f in to bypass the prescaler and powers down the prescaler. the output from the main counter chain, f p , is related to the vco frequency, f in , by the following equation: f p = f in / [10 x (m + 1) + a] (1) where a ? m + 1, 1 m 511 or f p = f in / [5 x (m + 1) + a] where a ? m + 1, 1 m 511 when the loop is locked, f in is related to the reference frequency, f r , by the following equation: f in = [10 x (m + 1) + a] x [f r / (r + 1)] (2) where a ? m + 1, 1 m 511 or f in = [5 x (m + 1) + a] x [f r / (r + 1)] where a ? m + 1, 1 m 511 a consequence of the upper limit on a is that: in integer-n mode, to obtain contiguous channels, f in must be = 90 x [fr / (r + 1)] with 10/11 modulus f in must be = 20 x [fr / (r + 1)] with 5/6 modulus the a counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in m. programming the m counter with the minimum allowed value of ?1? will result in a minimum m counter divide ration of ?2?. prescaler bypass mode setting pre_en ?high? allows f in to bypass and power down the prescaler. in this mode, the 5/6 or 10/11 prescaler and a register are not active, and the input vco frequency is divided by the m counter directly. the following equation relates f in to the reference frequency, f r : f in = (m + 1) x [f r / (r + 1)] (3) where 1 m 511 reference counter the reference counter chain divides the reference frequency, f r , down to the phase detector comparison frequency, f c . the output frequency of the 6-bit r counter is related to the reference frequency by the following equation: f c = f r / (r + 1) (4) where 0 r 63 note that programming r with ?0? will pass the reference frequency, f r , directly to the phase detector.
preliminary specification PE33241 page 9 of 13 document no. doc-15014-3 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. serial interface mode while the e_wr input is ?low? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 20 , is clocked serially into the primary register on the rising edge of sclk, msb (b 0 ) first. the contents from the primary register are transferred into the secondary register on the rising edge of s_wr according to the timing diagram shown in figure 5 . data is transferred to the counters as shown in table 7 . while the e_wr input is ?high? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 7 , is clocked serially into the enhancement register on the rising edge of sclk, msb (b 0 ) first. the enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially-entered data performed on the falling edge of e_wr according to the timing diagram shown in figure 5 . after the falling edge of e_wr, the data provides control bits as shown in table 8 with bit functionality enabled by asserting the enh input ?low?. direct interface mode direct interface mode is selected by setting the direct input ?high?. counter control bits are set directly at the pins as shown in table 7 and table 8 . msb (first in) (last in) lsb table 7. primary register programming table 8. enhancement register programming * serial data clocked serially on sclk rising edge while e_wr ?low? and captured in secondary register on s_wr rising edge * serial data clocked serially on sclk rising edge while e_wr ?high? and captured in the double buffer on e_wr falling edge. msb (first in) (last in) lsb interface mode enh r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 addr serial * 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 b 20 direct 1 r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 0 interface mode enh reserved reserved f p output power down counter load msel output f c output ld disable serial* 0 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 direct 0
preliminary specification PE33241 page 10 of 13 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. doc-15014-3 ultracmos ? rfic solutions figure 5. serial interface mode timing diagram t dhld t dsu t clkh t clkl t cwr t pw t wrc t ec t ce e_wr sdata sclk s_wr enhancement register the functions of the enhancement register bits ar e shown below with all bits active ?high?. table 9. enhancement register bit functionality ** program to 0 bit function description bit 0 reserve** reserved bit 1 reserve** reserved bit 2 f p output drives the m counter output onto the dout output bit 3 power down power down of all functions except programming interface bit 4 counter load immediate and cont inuous load of counter programming bit 5 msel output drives the intern al dual modulus prescaler modulus select (msel) onto the dout output bit 6 f c output drives the reference counter output onto the dout output bit 7 ld disable disables the ld pin for quieter operation
preliminary specification PE33241 page 11 of 13 document no. doc-15014-3 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. phase detector the phase detector is triggered by rising edges from the main counter (f p ) and the reference counter (f c ). it has two outputs, namely pd_ u , and pd_ d . if the divided vco leads the divided reference in phase or frequency (f p leads f c ), pd_ d pulses ?low?. if the divided reference leads the divided vco in phase or frequency (f r leads f p ), pd_ u pulses ?low?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . the phase detector gain is 400 mv/radian. pd_ u and pd_ d are designed to drive an active loop filter which controls the vco tune voltage. pd_ u pulses result in an increase in vco frequency and pd_ d results in a decrease in vco frequency. a lock detect output, ld is also provided, via the pin cext. cext is the logical ?nand? of pd_ u and pd_ d waveforms, which is driven through a series 2k ohm resistor. connecting cext to an external shunt capacitor provides integration. cext also drives the input of an internal inverting comparator with an open drain output. thus ld is an ?and? function of pd_ u and pd_ d . see figure 4 for a functional block diagram of this circuit.
preliminary specification PE33241 page 12 of 13 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. doc-15014-3 ultracmos ? rfic solutions 7.00 7.00 5.100.05 5.100.05 5.50 ref. 5.50 ref. 0.50 0.250.05 (x48) top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin #1 corner 0.203 0.90 max 0.05 0.400.05 (x48) chamfer 0.35 x 45 0.60 (x48) 0.30 (x48) 5.10 7.40 5.10 7.40 0.50 (x44) 1 12 13 24 25 36 37 48 figure 6. package drawing 48-lead 7x7 mm qfn 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 yyww pppppp llllll 33241 figure 7. top marking specifications line char code values description 1 1 ? symbol 1 7 logo symbol peregrine logo 2 8 logo symbol pin 1 designator peregrine logo 3 8 pppppp alphanumeric part number 4 8 llllll numeric lot number 5 8 yyww numeric date code 6 8 blank 181-0014 17-0011
preliminary specification PE33241 page 13 of 13 document no. doc-15014-3 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. table 10. ordering information order code description package shipping method PE33241mlda-f PE33241g-48qfn 7x7mm-2000c 48-lead 7x7 mm qfn tray ek33241-12 PE33241-48qfn 7x7mm-ek evaluation kit 1/box figure 8. tape and reel drawing tape feed direction device orientation in tape top of device pin 1 pocket nominal ao 7.25 bo 7.25 ko 1.10 notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com .

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